It is widely regarded that conventional semiconductor device scaling has ‘run-out’ of steam. Therefore, novel semiconductor device performance enhancements are necessary to continue to meet performance targets. Many performance enhancements attempt to utilize the effect that is generally referred to by those skilled in the art as “strained silicon”—that is, by applying a stress to the silicon lattice in the channel that the carrier mobility is enhanced. The enhanced carrier mobility, in turn, provides a substantial improvement in device speed.
Previous innovations have shown that performance enhancement can result from a uniaxial stress applied to the channel by use of a stressed nitride film deposited over a polysilicon gate structure. In such instances, a tensile gate liner is applied to nFET (field effect transistor) devices to improve electron mobility, while a compressive gate liner is applied to pFET devices. However, the stress in the channel of such FET devices strongly depends on the layout of the local contacts. In particular, as the local contact gets closer to the gate (hence less room for a stressed liner) the strain in the channel region decreases and the device performance suffers. This can be a challenge for circuit designers, for instance devices with different local contact designs will exhibit different device characteristics.
Also, the amount of stress in the channel of a FET depends on the nitride liner thickness. In principle, the thicker the nitride liner, the larger the stress value will be. However, nitride stress liners cannot be too thick (greater than 1000 Å) due to process limitations.
Despite the advances made to date using stress engineering, there is still a need to provide different means for achieving semiconductor device performance improvement from uniaxial strain which is independent on the layout of the local contacts and is not adversely affected by process limitations.